HD6413007F20 Datasheet, PDF (209/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from
ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
φ
Address bus
Bus cycle A Bus cycle B
T1 T2 T3 T1 T2
RD
HWR
Data bus
Data collision
Long buffer-off time
(a) Idle cycle not inserted
φ
Address bus
RD
HWR
Data bus
Bus cycle A Bus cycle B
T1 T2 T3 Ti T1 T2
(b) Idle cycle inserted
Figure 6.42 Example of Idle Cycle Operation (2) (ICIS0 = 1)
External Address Space Access Immediately after DRAM Space Access: If a DRAM space
access is followed by a non-DRAM external access when HWR and LWR have been selected as
the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted
regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.43 shows an example of the
operation.
This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and
LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to
the external device in the next cycle.
A T_i cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output
pins.
In the case of consecutive DRAM space access precharge cycles (Tp), the ICIS0 and ICIS1 bit
settings are invalid. In the case of consecutive reads between different areas, for example, if the
second access is a DRAM access, only a T_p cycle is inserted, and a T_i cycle is not. The timing in
this case is shown in figure 6.44.
Rev.5.00 Sep. 12, 2007 Page 179 of 764
REJ09B0396-0500