HD6413007F20 Datasheet, PDF (237/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.4 Operation
7.4.1 Overview
Table 7.5 summarizes the DMAC modes.
Table 7.5 DMAC Modes
Transfer Mode
Short address
mode
I/O mode
Idle mode
Repeat mode
Full address
mode
Normal mode
Block transfer mode
Activation
Compare match/input
capture A interrupt from
16-bit timer channels 0 to 2
Transmit-data-empty
and receive-data-full
interrupts from SCI
channel 0
Conversion-end interrupt
from A/D converter
External request
Auto-request
External request
Compare match/input
capture A interrupt from
ITU channels 0 to 2
Conversion-end interrupt
from A/D converter
External request
Notes
• Up to four channels
can operate
independently
• Only the B channels
support external requests
• A and B channels are
paired; up to two
channels are available
• Burst mode transfer or
cycle-steal mode transfer
can be selected for
autorequests.
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of transfers.
One 24-bit address and one 8-bit address are specified. The transfer direction is determined
automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The
transfer direction is determined automatically from the activation source.
Rev.5.00 Sep. 12, 2007 Page 207 of 764
REJ09B0396-0500