HD6413007F20 Datasheet, PDF (21/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6.11.2 BREQ Pin Input Timing ...................................................................................... 186
Section 7 DMA Controller................................................................................................ 187
7.1 Overview........................................................................................................................... 187
7.1.1 Features................................................................................................................ 187
7.1.2 Block Diagram ..................................................................................................... 188
7.1.3 Functional Overview............................................................................................ 188
7.1.4 Pin Configuration................................................................................................. 190
7.1.5 Register Configuration......................................................................................... 190
7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 191
7.2.1 Memory Address Registers (MAR) ..................................................................... 192
7.2.2 I/O Address Registers (IOAR) ............................................................................. 192
7.2.3 Execute Transfer Count Registers (ETCR) .......................................................... 193
7.2.4 Data Transfer Control Registers (DTCR) ............................................................ 195
7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 198
7.3.1 Memory Address Registers (MAR) ..................................................................... 198
7.3.2 I/O Address Registers (IOAR) ............................................................................. 198
7.3.3 Execute Transfer Count Registers (ETCR) .......................................................... 199
7.3.4 Data Transfer Control Registers (DTCR) ............................................................ 201
7.4 Operation........................................................................................................................... 207
7.4.1 Overview.............................................................................................................. 207
7.4.2 I/O Mode.............................................................................................................. 209
7.4.3 Idle Mode............................................................................................................. 211
7.4.4 Repeat Mode ........................................................................................................ 214
7.4.5 Normal Mode....................................................................................................... 218
7.4.6 Block Transfer Mode ........................................................................................... 221
7.4.7 DMAC Activation................................................................................................ 226
7.4.8 DMAC Bus Cycle ................................................................................................ 227
7.4.9 Multiple-Channel Operation ................................................................................ 233
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 234
7.4.11 NMI Interrupts and DMAC.................................................................................. 235
7.4.12 Aborting a DMAC Transfer................................................................................. 236
7.4.13 Exiting Full Address Mode .................................................................................. 237
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 238
7.5 Interrupts ........................................................................................................................... 238
7.6 Usage Notes ...................................................................................................................... 239
7.6.1 Note on Word Data Transfer................................................................................ 239
7.6.2 DMAC Self-Access ............................................................................................. 239
7.6.3 Longword Access to Memory Address Registers ................................................ 240
7.6.4 Note on Full Address Mode Setup ....................................................................... 240
Rev.5.00 Sep. 12, 2007 Page xix of xxviii
REJ09B0396-0500