HD6413007F20 Datasheet, PDF (147/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Bits 1 and 0⎯Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01
0
1
Bit 0
W00
0
1
0
1
Description
Program wait not inserted when external space area 0 is accessed
1 program wait state inserted when external space area 0 is accessed
2 program wait states inserted when external space area 0 is accessed
3 program wait states inserted when external space area 0 is accessed
(Initial value)
6.2.4 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A₂₃ to A₂₀ and
enables or disables release of the bus to an external device.
Bit
7
6
5
4
3
2
1
0
A23E A22E A21E A20E
⎯
⎯
⎯ BRLE
Modes ^{Initial value 1}
1
1
1
1
1
1
0
1 and 2 _{Read/Write ⎯}
⎯
⎯
⎯
⎯
⎯
⎯
R/W
Modes ^{Initial value 1}
1
1
0
1
1
1
0
3 and 4 _{Read/Write R/W}
R/W
R/W
⎯
⎯
⎯
⎯
R/W
Address 23 to 20 enable
These bits enable PA₇ to PA₄ to be
used for A₂₃ to A₂₀ address output
Reserved bits
Bus release enable
Enables or disables
release of the bus to
an external device
BRCR is initialized to H'FE in modes 1 and 2, and to H'EE in modes 3 and 4, by a reset and in
hardware standby mode. It is not initialized in software standby mode.
Rev.5.00 Sep. 12, 2007 Page 117 of 764
REJ09B0396-0500