HD6413007F20 Datasheet, PDF (154/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Bit 0⎯Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If
areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0
RFSHE
0
1
Description
RFSH pin refresh signal output disabled
(RFSH pin can be used as input/output port)
RFSH pin refresh signal output enabled
(Initial value)
6.2.8 DRAM Control Register B (DRCRB)
Bit
Initial value
Read/Write
7
6
5
4
3
MXC1 MXC0 CSEL RCYCE ⎯
0
0
0
0
1
R/W
R/W
R/W
R/W
⎯
2
TPC
0
R/W
1
RCW
0
R/W
0
RLW
0
R/W
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column
address bits for the DRAM interface, the column address strobe output pin, enabling or disabling
of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state
insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh
cycles.
DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.
Rev.5.00 Sep. 12, 2007 Page 124 of 764
REJ09B0396-0500