HD6413007F20 Datasheet, PDF (170/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
16-Bit, Three-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for
a 16-bit, three-state-access area. In these areas, the upper data bus (D₁₅ to D₈) is used in accesses to
even addresses and the lower data bus (D₇ to D₀) in accesses to odd addresses. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read access ^D15 ^{to D}8
D7 to D0
HWR
Write access
LWR
D15 to D8
D7 to D0
Even external address in area n
Valid
Invalid
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
Rev.5.00 Sep. 12, 2007 Page 140 of 764
REJ09B0396-0500