HD6413007F20 Datasheet, PDF (264/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
DMAC cycle
(channel 1)
CPU
cycle
DMAC cycle
(channel 0A)
CPU
cycle
DMAC cycle
(channel 1)
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂
φ
Address
bus
RD
HWR ,
LWR
Figure 7.19 Timing of Multiple-Channel Operations
7.4.10 External Bus Requests, DRAM Interface, and DMAC
During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer
of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus
right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a
burst transfer on channel 0.
DMAC cycle (channel 0)
Refresh
cycle
DMAC cycle (channel 0)
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
φ
Address
bus
RD
HWR
Figure 7.20 Bus Timing of DRAM Interface and DMAC
Rev.5.00 Sep. 12, 2007 Page 234 of 764
REJ09B0396-0500