HD6413007F20 Datasheet, PDF (446/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
12.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and
clock source.
Bit
7
6
5
4
OVF WT/IT TME
⎯
Initial value
0
0
0
1
Read/Write R/(W) ^* R/W R/W
⎯
3
2
1
0
⎯
CKS2 CKS1 CKS0
1
0
0
0
⎯
R/W
R/W
R/W
Clock select
These bits select the
TCNT clock source
Reserved bits
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register
Access.
* Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Bit 7⎯Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7
OVF
0
1
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
[Setting condition]
Set when TCNT changes from H'FF to H'00
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 416 of 764
REJ09B0396-0500