HD6413007F20 Datasheet, PDF (702/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
DTCR0B⎯Data Transfer Control Register 0B (cont) H'FFF2F
• Full address mode
Bit
7
6
DTME
⎯
5
DAID
4
DAIDE
3
TMS
2
DTS2B
1
DTS1B
0
DTS0B
Initial value
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
0
0
0
R/W
R/W
R/W
DMAC0
Data transfer master enable
0 Data transfer is disabled
1 Data transfer is enabled
Data transfer select 2B to 0B
Bit 2 Bit 1 Bit 0
DTS2B DTS1BDTS0B
Data Transfer Activation Source
Normal Mode
Block Transfer Mode
0
0
0 ^{Auto-request (burst mode)}
1 ^{Not available}
Compare match/input capture A
interrupt from 16-bit timer channel 0
Compare match/input capture A
interrupt from 16-bit timer channel 1
1
0 ^{Auto-request (cycle-steal mode)}
Compare match/input capture A
interrupt from 16-bit timer channel 2
1 Not available
0 Not available
0
1 Not available
1
0 Falling edge of DREQ input
1
1 Low level input at DREQ input
A/D converter conversion end interrupt
Not available
Not available
Falling edge of DREQ input
Not available
Transfer mode select
0 Destination is the block area in block transfer mode
1 Source is the block area in block transfer mode
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 5
DAID
0
1
Bit 4
DAIDE
Increment/Decrement Enable
0 MARB is held fixed
1 ^{Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer}
If DTSZ = 1, MARB is incremented by 2 after each transfer
0 MARB is held fixed
1 ^{Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer}
If DTSZ = 1, MARB is decremented by 2 after each transfer
Rev.5.00 Sep. 12, 2007 Page 672 of 764
REJ09B0396-0500