HD6413007F20 Datasheet, PDF (61/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

2. CPU
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2 Instructions and Addressing Modes
Addressing Modes
Function Instruction
#xx Rn
@
@
@
@
(d:16, (d:24, @ERn+/ @
@
@
(d:8, (d:16, @@
@ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 PC) PC) aa:8 ⎯
Data
MOV
BWL BWL BWL BWL BWL BWL
B
BWL BWL ⎯
⎯
⎯
⎯
transfer
POP, PUSH ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
WL
MOVFPE,
MOVTPE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Arithmetic ADD, CMP
BWL BWL ⎯
⎯
⎯
⎯
operations
SUB
WL BWL ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADDX, SUBX B
B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADDS, SUBS ⎯
L
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
INC, DEC
⎯
BWL ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAA, DAS
⎯
B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MULXU,
⎯
BW ⎯
⎯
⎯
⎯
MULXS,
DIVXU, DIVXS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NEG
⎯
BWL ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EXTU, EXTS ⎯
WL ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Logic
AND, OR, XOR ⎯
BWL ⎯
⎯
⎯
⎯
operations
NOT
⎯
BWL ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Shift instructions
⎯
BWL ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit manipulation
⎯
B
B
⎯
⎯
⎯
B
⎯
⎯
⎯
⎯
⎯
⎯
Branch
Bcc, BSR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
JMP, JSR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RTS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
System
control
TRAPA
RTE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SLEEP
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
LDC
B
B
W
W
W
W
⎯
W
W
⎯
⎯
⎯
STC
⎯
B
W
W
W
W
⎯
W
W
⎯
⎯
⎯
⎯
ANDC, ORC, B
XORC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NOP
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Block data transfer
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BW
Rev.5.00 Sep. 12, 2007 Page 31 of 764
REJ09B0396-0500