HD6413007F20 Datasheet, PDF (778/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix D Pin States
Hardware
Port Name
Standby
Pin Name Mode Reset Mode
Software Standby Mode Bus-Released State
Program
Execution
State
PB₅, PB₄
1 to 4 T
T
• CAS output*¹⁶
[SSOE = 0]
T
[SSOE = 1]
H
• Otherwise*¹⁷
Keep
• CAS output*¹⁶
T
• Otherwise*¹⁷
Keep
• CAS output
UCAS,
LCAS
• Otherwise
I/O port
PB₇, PB₆
1 to 4 T
T
Keep
Keep
I/O port
Legend:
H:
High
L:
Low
T:
High-impedance state
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. Low only when WDT overflow causes a reset.
2. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
cleared to 0.
3. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1.
4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 010, 100, or 101.
5. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 010, 100, or 101.
6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
cleared to 0.
7 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
set to 1.
8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1.
9. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared
to 0.
10. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 101.
11. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set
to 1.
12. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is
cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 748 of 764
REJ09B0396-0500