HD6413007F20 Datasheet, PDF (297/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

8.7.2 Register Configuration
Table 8.11 summarizes the registers of port A.
Table 8.11 Port A Registers
Address* Name
Abbreviation R/W
H'EE009
Port A data direction PADDR
W
register
H'FFFD9
Port A data register
PADR
R/W
Note: * Lower 20 bits of the address in advanced mode.
8. I/O Ports
Initial Value
Modes 1, 2 Modes 3, 4
H'00
H'80
H'00
H'00
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA₇DDR PA₆DDR PA₅DDR PA₄DDR PA₃DDR PA₂DDR PA₁DDR PA₀DDR
Modes ^{Initial value 1}
0
0
0
0
0
0
0
3, 4, _{Read/Write ⎯}
W
W
W
W
W
W
W
Modes Initial value 0
0
0
0
0
0
0
0
1, 2 _{Read/Write W}
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input
port if this bit is cleared to 0. In modes 3 and 4, PA₇DDR is fixed at 1 and PA₇ functions as an
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 (modes 1 and 2) or H'80 (modes 3 and 4) by a reset and in hardware
standby mode. In software standby mode it retains it previous setting. Therefore, if a transition is
made to software standby mode while a PADDR bit is set to 1, the corresponding pin maintains its
output state.
Rev.5.00 Sep. 12, 2007 Page 267 of 764
REJ09B0396-0500