HD6413007F20 Datasheet, PDF (357/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9. 16-Bit Timer
Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA₀, TIOCA₁,
and TIOCA₂. For further information on PWM mode, see section 9.4.4, PWM Mode.
Value of 16TCNT0 to 16TCNT2
Synchronous clearing by GRB0 compare match
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
H'0000
TIOCA₀
TIOCA₁
TIOCA₂
Figure 9.25 Synchronization (Example)
9.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a
PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can
be selected in all channels (0 to 2).
Table 9.4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
Rev.5.00 Sep. 12, 2007 Page 327 of 764
REJ09B0396-0500