HD6413007F20 Datasheet, PDF (678/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
SYSCR⎯System Control Register
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
H'EE012
System control
3
2
1
0
UE NMIEG SSOE RAME
1
0
0
1
R/W
R/W
R/W R/W
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled
Software standby output port enable
In software standby mode,
all address bus and bus
0 _{control signals are high-}
impedance
In software standby mode,
address bus retains output
1 ^{state and bus control}
signals are fixed high
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6
STS2
0
1
Bit 5
STS1
0
1
0
1
Bit 4
STS0
0
1
0
1
0
1
0
1
Standby Timer
Waiting Time = 8,192 states
Waiting Time = 16,384 states
Waiting Time = 32,768 states
Waiting Time = 65,536 states
Waiting Time = 131,072 states
Waiting Time = 26,2144 states
Waiting Time = 1,024 states
Illegal setting
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
Rev.5.00 Sep. 12, 2007 Page 648 of 764
REJ09B0396-0500