HD6413007F20 Datasheet, PDF (434/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
Bit 0⎯Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP₃ to TP₀).
Bit 0
G0NOV
0
1
Description
Normal TPC output in group 0 (output values change at
compare match A in the selected 16-bit timer channel)
Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
11.3 Operation
11.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating
conditions.
DDR
Q
NDER
Q
Output trigger signal
TPC output pin
C
Q DR D
Q NDR D
Internal
data bus
Figure 11.2 TPC Output Operation
Rev.5.00 Sep. 12, 2007 Page 404 of 764
REJ09B0396-0500