HD6413007F20 Datasheet, PDF (169/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
8-Bit, Two-State-Access Areas: Figure 6.8 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper data bus (D₁₅ to D₈) is used in accesses to these areas. The LWR
pin is always high. Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read access D15 to D8
D7 to D0
HWR
Write access
LWR
D15 to D8
D7 to D0
External address in area n
Valid
Invalid
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.8 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
Rev.5.00 Sep. 12, 2007 Page 139 of 764
REJ09B0396-0500