HD6413007F20 Datasheet, PDF (575/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

17. RAM
Bit 0⎯RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
17.3 Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF20 to
H'FFF1F in the H8/3007 in modes 1 and 2, and to addresses H'FFEF20 to H'FFFF1F in the
H8/3007 in modes 3 and 4, are directed to the on-chip RAM. In the H8/3006, accesses to
addresses H'FF720 to H'FFF1F in modes 1 and 2, to addresses H'FFF720 to H'FFFF1F in modes 3
and 4, are directed to the on-chip RAM. In modes 1 to 4, when the RAME bit is cleared to 0, the
off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
Rev.5.00 Sep. 12, 2007 Page 545 of 764
REJ09B0396-0500