HD6413007F20 Datasheet, PDF (219/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
Table 7.1 DMAC Functional Overview
Address
Reg. Length
Transfer Mode
Activation
Destina-
Source tion
Short I/O mode
• Compare match/input
24
8
address _{• Transfers one byte or one word}
mode
per request
capture A interrupts from
16-bit timer channels 0 to 2
• Increments or decrements the memory ^{• Transmit-data-empty}
address by 1 or 2
interrupt from SCI channel 0
• Executes 1 to 65,536 transfers
Idle mode
• Conversion-end interrupt 8
24
• Transfers one byte or one word per
from A/D converter
request
• Receive-data-full interrupt
• Holds the memory address fixed
from SCI channel 0
• Executes 1 to 65,536 transfers
• External request
24
8
Repeat mode
• Transfers one byte or one word per
request
• Increments or decrements the memory
address by 1 or 2
• Executes a specified number (1 to 255)
of transfers, then returns to the initial
state and continues
Full
address
mode
Normal mode
• Auto-request
⎯ Retains the transfer request
internally
• Auto-request
• External request
24
24
⎯ Executes a specified number(1 to
65,536) of transfers continuously
⎯ Selection of burst mode or cycle-
steal mode
• External request
⎯ Transfers one byte or one word per
request
⎯ Executes 1 to 65,536 transfers
Block transfer
• Compare match/ input
24
24
• Transfers one block of a specified size
per request
capture A interrupts from
16-bit timer channels 0 to 2
• Executes 1 to 65,536 transfers
• External request
• Allows either the source or destination to ^{• Conversion-end interrupt}
be a fixed block area
from A/D converter
• Block size can be 1 to 255 bytes or
words
Rev.5.00 Sep. 12, 2007 Page 189 of 764
REJ09B0396-0500