HD6413007F20 Datasheet, PDF (157/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.2.9 Refresh Timer Control/Status Register (RTMCSR)
Bit
7
6
5
4
3
2
1
0
CMF CMIE CKS2 CKS1 CKS0
⎯
⎯
⎯
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/(W)* R/W
R/W
R/W
R/W
⎯
⎯
⎯
RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When
the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.
Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are
initialized to 0 by a reset and in hardware standby mode; they are not initialized in software
standby mode.
Note: Only 0 can be written to clear the flag.
Bit 7⎯Compare Match Flag (CMF): Status flag that indicates a match between the values of
RTCNT and RTCOR.
Bit 7
CMF
0
1
Description
[Clearing conditions]
• When the chip is reset and in standby mode
• Read CMF when CMF = 1, then write 0 in CMF
[Setting condition]
When RTCNT = RTCOR
(Initial value)
Bit 6⎯Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
any of areas 2 to 5 is designated as DRAM space.
Bit 6
CMIE
0
1
Description
The CMI interrupt requested by CMF is disabled
The CMI interrupt requested by CMF is enabled
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 127 of 764
REJ09B0396-0500