HD6413007F20 Datasheet, PDF (514/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

13. Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 − ¹ ) − (L − 0.5) F − ^{D − 0.5} (1 + F) × 100%
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (L = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
. . . . . . . . (1)
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = (0.5 − ¹
) × 100%
2 × 16
= 46.875%
. . . . . . . . (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC:
• When an external clock source is used for the serial clock, after the DMAC updates TDR,
allow an inversion of at least five system clock (φ) cycles before input of the serial clock to
start transmitting. If the serial clock is input within four states of the TDR update, a
malfunction may occur. (See figure 13.22)
• To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full
interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
Rev.5.00 Sep. 12, 2007 Page 484 of 764
REJ09B0396-0500