HD6413007F20 Datasheet, PDF (180/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM
space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is
inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,
for details.
Tp
Tr
Tc1
Tc2
φ
A23 to A0
AS
Row
High
Column
CSn (RAS)
Read access
PB4 /PB5
(UCAS / LCAS)
RD(WE)
High
D15 to D0
Write access
PB4 /PB5
(UCAS / LCAS)
RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.16 Basic Access Timing (CSEL = 0 in DRCRB)
Rev.5.00 Sep. 12, 2007 Page 150 of 764
REJ09B0396-0500