HD6413007F20 Datasheet, PDF (405/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
⎯ OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
H'FF to H'00).
Compare Match Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
Channels 0 and 1 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
Channels 2 and 3 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
Caution: Do not set 16-bit count mode and compare match count mode simultaneously within the
same group, as the 8TCNT input clock will not be generated and the counters will not operate.
10.4.6 Input Capture Setting
The 8TCNT value can be transferred to TCORB on detection of an input edge on the input
capture/output compare pin (TMIO₁ or TMIO₃). Rising edge, falling edge, or both edge detection
can be selected. In 16-bit count mode, 16-bit input capture can be used.
Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation)
• Channel 1:
⎯ Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO₁) with bits OIS3 and OIS2 in 8TCSR1.
⎯ Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
• Channel 3:
⎯ Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO₃) with bits OIS3 and OIS2 in 8TCSR3.
Rev.5.00 Sep. 12, 2007 Page 375 of 764
REJ09B0396-0500