HD6413007F20 Datasheet, PDF (206/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.8 Burst ROM Interface
6.8.1 Overview
With the H8/3006 and H8/3007, external space area 0 can be designated as burst ROM space, and
burst ROM space interfacing can be performed. The burst ROM interface enables ROM with burst
access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means
of the BROME bit in BCR.
Continuous burst access of a maximum or four or eight words can be performed on external space
area 0. Two or three states can be selected for burst access.
6.8.2 Basic Timing
The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface
is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states
can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle.
Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and
burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access
states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1.
The basic access timing for burst ROM space is shown in figure 6.40.
Rev.5.00 Sep. 12, 2007 Page 176 of 764
REJ09B0396-0500