HD6413007F20 Datasheet, PDF (210/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Bus cycle A
(DRAM access cycle) Bus cycle B
Bus cycle A
(DRAM access cycle) Bus cycle B
φ
Address bus
T_p T_r T_c1 T_c2 T₁ T₂
φ
Address bus
T_p T_r T_c1 T_c2 T_i T₁ T₂
HWR/LWR
(UCAS/LCAS)
CSn
HWR/LWR
(UCAS/LCAS)
CSn
Simultaneous change of
HWR/LWR and CSn
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
φ
Address bus
RD
UCAS/LCAS
Address bus
External read
T₁ T₂ T₃
DRAM space read
T_p T_r T_c1 T_c2
Figure 6.44 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.45.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
Rev.5.00 Sep. 12, 2007 Page 180 of 764
REJ09B0396-0500