HD6413007F20 Datasheet, PDF (444/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
Interrupt signal
Interrupt
(interval timer) ^control
TCNT
TCSR
RSTCSR
Reset
(internal, external)
Reset control
Clock
Clock
selector
Legend:
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Figure 12.1 WDT Block Diagram
Read/
write
control
Internal
data bus
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
12.1.3 Pin Configuration
Table 12.1 describes the WDT output pin.
Table 12.1 WDT Pin
Name
Abbreviation
Reset output RESO
Note: * Open-drain output.
I/O
Output*
Function
External output of the watchdog timer reset signal
Rev.5.00 Sep. 12, 2007 Page 414 of 764
REJ09B0396-0500