HD6413007F20 Datasheet, PDF (201/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
φ
RTCNT
N
H'00
RTCOR
N
Compare match
signal
CMF
Figure 6.36 Timing of CMF Flag Setting
Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate
in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are
initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to
software standby mode.
Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T₃ state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
performed. See figure 6.37.
T1
T2
T3
φ
Address bus
Internal write signal
RTCNT address
Counter clear signal
RTCNT
N
H'00
Figure 6.37 Contention between RTCNT Write and Clear
Rev.5.00 Sep. 12, 2007 Page 171 of 764
REJ09B0396-0500