HD6413007F20 Datasheet, PDF (643/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Addressing Mode and
Instruction Length (bytes)
Appendix A Instruction Set
No. of
States*¹
Mnemonic
DIVXU. W Rs, ERd W
2
DIVXS. B Rs, Rd
B
4
DIVXS. W Rs, ERd W
4
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
B2
B
2
W4
W
2
L6
L
2
B
2
W
2
L
2
W
2
EXTU.L ERd
L
2
EXTS.W Rd
W
2
EXTS.L ERd
L
2
Condition Code
Operation
I HNZVC
ERd32 ÷ Rs16 → ERd32 ⎯ ⎯ (6) (7) ⎯ ⎯ 22
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
⎯ ⎯ (8) (7) ⎯ ⎯ 16
ERd32 ÷ Rs16 → ERd32 ⎯ ⎯ (8) (7) ⎯ ⎯ 24
(Ed: remainder,
Rd: quotient)
(signed division)
Rd8–#xx:8
⎯
2
Rd8–Rs8
⎯
2
Rd16–#xx:16
⎯ (1)
4
Rd16–Rs16
⎯ (1)
2
ERd32–#xx:32
⎯ (2)
6
ERd32–ERs32
⎯ (2)
2
0–Rd8 → Rd8
⎯
2
0–Rd16 → Rd16
⎯
2
0–ERd32 → ERd32
⎯
2
0 → (<bits 15 to 8>
of Rd16)
⎯⎯ 0
0⎯ 2
0 → (<bits 31 to 16>
of ERd32)
⎯⎯ 0
0⎯ 2
(<bit 7> of Rd16) →
⎯⎯
(<bits 15 to 8> of Rd16)
0⎯ 2
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
⎯⎯
0⎯ 2
Rev.5.00 Sep. 12, 2007 Page 613 of 764
REJ09B0396-0500