HD6413007F20 Datasheet, PDF (70/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

2. CPU
Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA ⎯
Starts trap-instruction exception handling
RTE
⎯
Returns from an exception-handling routine
SLEEP ⎯
Causes a transition to the power-down state
LDC
B/W (EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data is
read by word access.
STC
B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP
⎯
PC + 2 → PC
Only increments the program counter.
Note:
* Size refers to the operand size.
B: Byte
W: Word
Rev.5.00 Sep. 12, 2007 Page 40 of 764
REJ09B0396-0500