HD6413007F20 Datasheet, PDF (181/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.5.7 Precharge State Control
In the H8/3006 and H8/3007, provision is made for the DRAM RAS precharge time by always
inserting one RAS precharge state (T_p) when DRAM space is accessed. This can be changed to
two T_p states by setting the TPC bit to 1 in DRCRB. The optimum number of T_p cycles should be
set according to the DRAM connected and the operating frequency of the H8/3006 and H8/3007
chip. Figure 6.17 shows the timing when two T_p states are inserted.
When the TCP bit is set to 1, two T_p states are also used for CAS-before-RAS refresh cycles.
Tp1
Tp2
Tr
Tc1
Tc2
φ
A23 to A0
AS
Row
High
Column
Read access
CSn (RAS)
PB4 /PB5
(UCAS /LCAS)
RD(WE)
High
D15 to D0
PB4 /PB5
(UCAS /LCAS)
Write access
RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.17 Timing with Two Precharge States (CSEL = 0 in DRCRB)
Rev.5.00 Sep. 12, 2007 Page 151 of 764
REJ09B0396-0500