HD6413007F20 Datasheet, PDF (191/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
φ
RTCNT
N
H'00
RTCOR
N
Refresh request signal
and CMF bit setting signal
Figure 6.25 Compare Match Timing
TRp
TR1
TR2
φ
Address bus
Area 2 start address
CSn(RAS)
PB4/PB5
(UCAS/LCAS)
RD(WE)
RFSH
AS
High
High
Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T_RP) state,
and two RAS output cycle (T_R1, T_R2) states. Either one or two states can be selected for the RAS
precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one
cycle. This does not affect the timing of UCAS and LCAS output.
Rev.5.00 Sep. 12, 2007 Page 161 of 764
REJ09B0396-0500