HD6413007F20 Datasheet, PDF (450/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
Writing 0 in WRST bit
15
87
0
Address H'FFF8E*
H'A5
H'00
Writing to RSTOE bit
15
Address H'FFF8E*
H'5A
87
0
Write data
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR: For reads of TCNT, TCSR, and RSTCSR, address
H'FFF8C is assigned to TCSR, address H'FFF8D to TCNT, and address H'FFF8F to RSTCSR.
These registers are therefore read like other registers. Byte transfer instructions can be used for
reading. Table 12.3 lists the read addresses of TCNT, TCSR, and RSTCSR.
Table 12.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address*
Register
H'FFF8C
TCSR
H'FFF8D
TCNT
H'FFF8F
RSTCSR
Note: * Lower 20 bits of the address in advanced mode.
12.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
12.3.1 Watchdog Timer Operation
Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3006 and H8/3007 are internally reset for a duration
of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
Rev.5.00 Sep. 12, 2007 Page 420 of 764
REJ09B0396-0500