HD6413007F20 Datasheet, PDF (152/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.2.7 DRAM Control Register A (DRCRA)
Bit
Initial value
Read/Write
7
6
5
4
DRAS2 DRAS1 DRAS0 ⎯
0
0
0
1
R/W
R/W
R/W
⎯
3
2
1
0
BE
RDM SRFMD RFSHE
0
0
0
0
R/W
R/W
R/W
R/W
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface
function, and the access mode, and enables or disables self-refreshing and refresh pin output.
DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5⎯DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are
to function as DRAM interface areas (DRAM space), and at the same time select the RAS output
pin corresponding to each DRAM space.
Description
Bit 7 Bit 6 Bit 5
DRAS2 DRAS1 DRAS0 Area 5
Area 4
Area 3
Area 2
0
0
0
Normal
Normal
Normal
Normal
1
Note:
1
Normal
Normal
Normal
DRAM space
(CS )
2
1
0
Normal
Normal
DRAM space
(CS₃)
DRAM space
(CS₂)
1
Normal
Normal
DRAM space (CS₂)*
0
0
Normal
DRAM space
(CS₄)
DRAM space
(CS₃)
DRAM space
(CS₂)
1
DRAM space DRAM space DRAM space DRAM space
(CS₅)
(CS₄)
(CS₃)
(CS₂)
1
0
DRAM space (CS₄)*
DRAM space (CS₂)*
1
DRAM space (CS₂)*
* A single CSn pin serves as a common RAS output pin for a number of areas. Unused
CSn pins can be used as input/output ports.
When any of bits DRAS2 to DRAS0 is set to 1, it is not possible to write to DRCRB, RTMCSR,
RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 122 of 764
REJ09B0396-0500