HD6413007F20 Datasheet, PDF (525/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

14. Smart Card Interface
Bits 1 and 0⎯Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
0
1
Bit 1
CKE1
0
1
Bit 0
CKE0
0
1
0
1
0
1
Description
Internal clock/SCK pin is I/O port
(Initial value)
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at low output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at high output
Internal clock/SCK pin is clock output
14.3 Operation
14.3.1 Overview
The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of
one bit) is provided between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for a1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
14.3.2 Pin Connections
Figure 14.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to V_CC with a resistor.
Rev.5.00 Sep. 12, 2007 Page 495 of 764
REJ09B0396-0500