HD6413007F20 Datasheet, PDF (577/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

18. Clock Pulse Generator
Section 18 Clock Pulse Generator
18.1 Overview
The H8/3006 and H8/3007 have a built-in clock pulse generator (CPG) that generates the system
clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency
divider divides the clock frequency to generate the system clock (φ). The system clock is output at
the φ pin*¹ and furnished as a master clock to prescalers that supply clock signals to the on-chip
supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the
frequency divider by settings in a division control register (DIVCR)*². Power consumption in the
chip is reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 19.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
where, EXTAL:Frequency of crystal resonator or external clock signal
n:
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
18.1.1 Block Diagram
Figure 18.1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL
Oscillator
Duty
adjustment
circuit
Frequency
divider
CPG
Prescalers
Division
control
register
Data bus
φ φ/2 to φ/4096
Figure 18.1 Block Diagram of Clock Pulse Generator
Rev.5.00 Sep. 12, 2007 Page 547 of 764
REJ09B0396-0500