HD6413007F20 Datasheet, PDF (82/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

2. CPU
Exception
sources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2.12 Classification of Exception Sources
Bus request
End of bus release
End of bus
Program execution state
release
Bus
request
Exception
Bus-released state
handling source
SLEEP
instruction
with SSBY = 0
Sleep mode
End of
exception
handling
Exception-handling state
Interrupt source
NMI, IRQ₀, IRQ ₁,
or IRQ ₂ interrupt
SLEEP instruction
with SSBY = 1
Software standby mode
RES = High
Reset state ^*1
STBY = High, RES = Low
Hardware standby mode ^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. _{From any state, a transition to hardware standby mode occurs when STBY goes low.}
Figure 2.13 State Transitions
Rev.5.00 Sep. 12, 2007 Page 52 of 764
REJ09B0396-0500