HD6413007F20 Datasheet, PDF (167/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Areas
2
to
5:
When
area
2
to
5
external
space
is
accessed,
signals
CS
2
to
CS
5
can
be
output.
Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface,
signals CS₂ to CS₅ are used as RAS signals.
The size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Area 7: Area 7 includes the on-chip RAM and registers. The space excluding the on-chip RAM
and registers is external space. The on-chip RAM is enabled when the RAME bit in the system
control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is
disabled and the corresponding space becomes external space .
When area 7 external space is accessed, the CS₇ signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Rev.5.00 Sep. 12, 2007 Page 137 of 764
REJ09B0396-0500