HD6413007F20 Datasheet, PDF (227/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
Bit 3⎯Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 to 0⎯Data Transfer Select (DTS2 to DTS0): These bits select the data transfer activation
source. Some of the selectable sources differ between channels A and B.*
Note: * See section 7.3.4, Data Transfer Control Registers (DTCR).
Bit 2
DTS2
0
1
Bit 1
DTS1
0
1
0
1
Bit 0
DTS0
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from 16-bit timer channel 0
(Initial value)
Compare match/input capture A interrupt from 16-bit timer channel 1
Compare match/input capture A interrupt from 16-bit timer channel 2
Conversion-end interrupt from A/D converter
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 7.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Rev.5.00 Sep. 12, 2007 Page 197 of 764
REJ09B0396-0500