HD6413007F20 Datasheet, PDF (724/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
TCNT⎯Timer Counter
Bit
7
6
H'FFF8D (read), H'FFF8C (write)
5
4
3
2
1
WDT
0
Initial value
0
Read/Write
R/W
0
R/W
0
R/W
0
0
R/W
R/W
Count value
0
0
0
R/W
R/W
R/W
RSTCSR⎯Reset Control/Status Register
Bit
7
6
5
WRST RSTOE
⎯
Initial value
0
0
1
Read/Write R/(W)*
R/W
⎯
H'FFF8F (read), H'FFF8E (write) WDT
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
Reset output enable
0 External output of reset signal is disabled
1 External output of reset signal is enabled
Watchdog timer reset
0 ^{[Clearing conditions]}
• Reset signal at RES pin
• Read WRST when WRST = 1, then write 0 in WRST
[Setting condition]
1 _{TCNT overflow generates a reset signal}
Note: * Only 0 can be written in bit 7, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 694 of 764
REJ09B0396-0500