HD6413007F20 Datasheet, PDF (13/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Item
Page
10.4.5 Operation with 373
Cascaded Connection
375
10.4.6 Input Capture 376
Setting
11.3.3 Normal TPC 406
Output
Figure 11.4 Setup
Procedure for Normal
TPC Output (Example)
Figure 11.5 Normal 407
TPC Output Example
(Five-Phase Pulse
Output)
13.1 Overview
425
13.2.3 Transmit Shift 431
Register (TSR)
13.3.4 Synchronous 478
Operation
Revision (See Manual for Details)
Description amended
…In this case, the timer operates as below. Similarly, if bits
CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the
8-bit timers of channels 2 and 3 are cascaded. …
Description amended
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter
(8TCNT3) overflows (from H'FF to H'00).
Note added
Note: When TCORB1 in channel 1 is used for input capture,
TCORB0 in channel 0 cannot be used as a compare
match register.
Similarly, when TCORB3 in channel 3 is used for input
capture, TCORB2 in channel 2 cannot be used as a
compare match register.
Description amended
4. Enable the IMFA interrupt in TISRA.
The DMAC can also be set up to transfer data to the next
data register.
Description amended
• The 16-bit timer channel to be used as the output trigger
channel is set up so that GRA is an output compare register
and the counter will be cleared by compare match A. The
trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare
match A interrupt.
Description amended
The H8/3006 and H8/3007 have a serial communication
interface (SCI) with three independent channels. All three
channels have identical functions. The SCI can communicate in
both asynchronous and synchronous mode. It also has a
multiprocessor communication function for serial
communication among two or more processors.
Description amended
… If the TDRE flag is set to 1 in SSR, however, the SCI does
not load the TDR contents into TSR. The CPU cannot read or
write TSR directly.
Description amended
• The SCI synchronizes with the serial clock input or output and
performs receive operation.
Rev.5.00 Sep. 12, 2007 Page xi of xxviii
REJ09B0396-0500