HD6413007F20 Datasheet, PDF (331/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9. 16-Bit Timer
Bit 5⎯Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables
the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
Bit 5
IMIEB1
0
1
Description
IMIB1 interrupt requested by IMFB1 flag is disabled
IMIB1 interrupt requested by IMFB1 flag is enabled
(Initial value)
Bit 4⎯Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables
the interrupt requested by the IMFB0 flag when IMFB0 is set to 1.
Bit 4
IMIEB0
0
1
Description
IMIB0 interrupt requested by IMFB0 flag is disabled
IMIB0 interrupt requested by IMFB0 flag is enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2
compare match or input capture events.
Bit 2
IMFB2
0
1
Description
[Clearing condition]
Read IMFB2 when IMFB2 =1, then write 0 in IMFB2.
(Initial value)
[Setting conditions]
• 16TCNT2 = GRB2 when GRB2 functions as an output compare register.
• 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2
functions as an input capture register.
Rev.5.00 Sep. 12, 2007 Page 301 of 764
REJ09B0396-0500