HD6413007F20 Datasheet, PDF (447/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
Bit 6⎯Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT
0
1
Description
Interval timer: requests interval timer interrupts
Watchdog timer: generates a reset signal
(Initial value)
Bit 5⎯Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear
the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1,
TME should be cleared to 0.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and halted
TCNT is counting
(Initial value)
Bits 4 and 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0⎯Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 417 of 764
REJ09B0396-0500