HD6413007F20 Datasheet, PDF (155/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Bits 7 and 6⎯Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row
address/column address multiplexing method used on the DRAM interface. In burst operation, the
row address used for comparison is determined by the setting of these bits and the bus width of the
relevant area set in ABWCR.
Bit 7
MXC1
0
Bit 6
MXC0
0
Description
Column address: 8 bits
Compared address:
Modes 1, 2
Modes 3, 4
1
Column address: 9 bits
Compared address:
Modes 1, 2
Modes 3, 4
1
0
Column address: 10 bits
Compared address:
Modes 1, 2
Modes 3, 4
1
Illegal setting
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
A₁₉ to A₈
A₁₉ to A₉
A to A
23
8
A to A
23
9
A to A
19
9
A₁₉ to A₁₀
A₂₃ to A₉
A₂₃ to A₁₀
A₁₉ to A₁₀
A₁₉ to A₁₁
A₂₃ to A₁₀
A to A
23
11
Bit 5⎯CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2
to 5 are designated as DRAM space.
Bit 5
CSEL
0
1
Description
PB4 and PB5 selected as UCAS and LCAS output pins
HWR and LWR selected as UCAS and LCAS output pins
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 125 of 764
REJ09B0396-0500