HD6413007F20 Datasheet, PDF (395/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
TCORB0 and TCORB2 function as compare match registers regardless of the setting of bit 4 of
8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1 Bit 3
(8TCSR3) OIS3
0
0
1
1
0
1
Bit 2
OIS2
0
1
0
1
0
1
0
1
Description
No change when compare match B occurs
(Initial value)
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0⎯Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
Bit 0
OS0
0
1
0
1
Description
No change when compare match A occurs
(Initial value)
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Rev.5.00 Sep. 12, 2007 Page 365 of 764
REJ09B0396-0500