HD6413007F20 Datasheet, PDF (403/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow
signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in
this case.
φ
8TCNT
Overflow signal
H'FF
H'00
OVF
Figure 10.16 Timing of OVF Setting
10.4.5 Operation with Cascaded Connection
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit count mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). In this case, the timer operates as below. Similarly, if bits CKS2 to
CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are
cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit count
mode), or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match
count mode). Timer operation in these cases is described below.
16-Bit Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
⎯ Setting when Compare Match Occurs
• The CMF flag is set to 1 in 8TCR0 when a 16-bit compare match occurs.
• The CMF flag is set to 1 in 8TCR1 when a lower 8-bit compare match occurs.
• TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
accordance with the 16-bit compare match conditions.
• TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
accordance with the lower 8-bit compare match conditions.
Rev.5.00 Sep. 12, 2007 Page 373 of 764
REJ09B0396-0500