HD6413007F20 Datasheet, PDF (523/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

14. Smart Card Interface
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7,
Serial Status Register (SSR). The setting conditions for transmit end (TEND, bit 2), however, are
modified as follows.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing conditions]
• Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
• The DMAC writes data in TDR.
1
End of transmission
[Setting conditions]
(Initial value)
• The chip is reset or enters standby mode.
• The TE bit and FER/ERS bit are both cleared to 0 in SCR.
• TDRE is 1 and ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial
character is transmitted (normal transmission).
Note: An etu (elementary time unit) is the time needed to transmit one bit.
Rev.5.00 Sep. 12, 2007 Page 493 of 764
REJ09B0396-0500