HD6413007F20 Datasheet, PDF (248/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.4.5 Normal Mode
In normal mode, the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 7.9 indicates the register functions in I/O mode.
Table 7.9 Register Functions in Normal Mode
Register
23
MARA
Function
0 Source address
register
23
MARB
0 Destination
address register
15
ETCRA
0 Transfer counter
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
Initial Setting
Operation
Transfer source
start address
Incremented or
decremented once per
transfer, or held fixed
Transfer destination Incremented or
start address
decremented once per
transfer, or held fixed
Number of
transfers
Decremented once per
transfer
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer
count is 65,536, obtained by setting ETCRA to H'0000.
Rev.5.00 Sep. 12, 2007 Page 218 of 764
REJ09B0396-0500