HD6413007F20 Datasheet, PDF (407/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts
(TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts.
Table 10.6 lists the interrupt sources.
Table 10.6 8-Bit Timer Interrupt Sources
Channel
0
1
Interrupt Source
CMIA0
CMIB0
CMIA1/CMIB1
0, 1
TOVI0/TOVI1
2
CMIA2
CMIB2
3
CMIA3/CMIB3
2, 3
TOVI2/TOVI3
Description
TCORA0 compare match
TCORB0 compare match/input capture
TCORA1 compare match, or TCORB1 compare match/input
capture
Counter 0 or counter 1 overflow
TCORA2 compare match
TCORB2 compare match/input capture
TCORA3 compare match, or TCORB3 compare match/input
capture
Counter 2 or counter 3 overflow
10.5.2 A/D Converter Activation
The A/D converter can only be activated by channel 0 compare match A.
When the CMFA flag in 8TCSR0 is set to 1 and the ADTE bit is also set to 1, activation of the
A/D converter will be requested on generation of channel 0 compare match A. If the TRGE bit in
ADCR is set to 1 at this time, the A/D converter will be activated. When ADTE bit in 8TCSR0 is
set to 1, the A/D converter external trigger pin (ADTRG) input is disabled.
10.6 8-Bit Timer Application Example
Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty
cycle. The settings for this example are as follows:
• Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a
TCORA compare match.
• Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA
compare match and 0 is output on a TCORB compare match.
The above settings enable a waveform with the cycle determined by TCORA and the pulse width
detected by TCORB to be output without software intervention.
Rev.5.00 Sep. 12, 2007 Page 377 of 764
REJ09B0396-0500