HD64F3039F18 Datasheet, PDF (84/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 3 MCU Operating Modes
3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3039 Group.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 UE NMIEG — RAME
0
0
0
0
1
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
Selects the valid edge
of the NMI input
User bit enable
Selects whether to use UI bit in CCR
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 17, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at
Rev.3.00 Mar. 26, 2007 Page 60 of 682
REJ09B0353-0300