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| HD64F3039F18 Datasheet, PDF (30/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series | |||
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Section 1 Overview
1.2 Block Diagram
Figure 1.1 shows an internal block diagram of the H8/3039 Group.
MD2
MD1
MD0
EXTAL
XTAL
Ï
STBY
RES
RESO/FWE*
NMI
P65/WR
P64/RD
P63/AS
P60/WAIT
P81/IRQ1
P80/IRQ0
Port 3
Address bus
Data bus (upper)
Data bus (lower)
H8/300H CPU
P53/A19
P52/A18
P51/A17
P50/A16
ROM
(Flash memory,
mask ROM)
Interrupt
controller
RAM
16-bit
integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
Watchdog
timer
(WDT)
Serial
communication
interface
(SCI) Ã 2 channel
A/D converter
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
Port B
Port A
Port 7
Note: * Mask ROM: RESO
Flash memory: FWE
Figure 1.1 Block Diagram
Rev.3.00 Mar. 26, 2007 Page 6 of 682
REJ09B0353-0300
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