HD64F3039F18 Datasheet, PDF (411/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
16 clocks
Internal
base clock
8 clocks
0
7
15 0
7
15 0
Receive data
(RxD)
Start bit
D₀
D₁
Synchronization
sampling timing
Data sampling
timing
Figure 11.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = | ( 0.5 – ¹ ) – (L – 0.5) F ^{| D – 0.5 |} (1 + F) | × 100% ..........(1)
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
When D = 0.5, F = 0:
M = [0.5 – 1/(2 × 16)] × 100%
= 46.875%..........................................................................................(2)
This is a theoretical value. A reasonable margin to allow in system design is 20% to 30%.
Rev.3.00 Mar. 26, 2007 Page 387 of 682
REJ09B0353-0300